The present device relates generally to semiconductor devices and, more particularly, to semiconductor devices and their manufacture involving the protection of circuitry in the device.
In recent years, the semiconductor industry has realized tremendous advances in technology which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A requirement of such high-density and high functionality in semiconductor devices has been the demand for increased density of individual circuitry within the chip. The increased density permits shorter electrical connections between the devices than possible in chips manufactured with circuitry in a less-dense arrangement.
A by-product of increased circuit density and decreased chip size is an increase in operating conditions that can adversely affect the performance of the device and damage circuitry therein. One such operating condition involves electrostatic discharge (ESD). ESD is a condition that can occur in conjunction with various device operations, and can potentially cause harm to circuitry. For instance, operational conditions that are outside of normal conditions, such as excess static charge in the device, can cause ESD during power-up and power-down on standard digital CMOS processes. Voltages and/or currents resulting from the excess static charge present during these and other processes can reach levels that are much higher than normal operating levels for circuitry in a semiconductor device. When the static charge is applied to device circuitry, the circuit operation can be affected. In addition, when voltage and/or current resulting from the ESD is high enough, the circuitry can be damaged.
Another operating condition that can cause problems with semiconductor devices is known as xe2x80x9clatch-up.xe2x80x9d Latch-up is an undesirable and sometimes self-destructive phenomenon that occurs when an inadvertent low-resistance path is created between power supply nodes (often referred to as VDD and VSS) in a semiconductor device. An inadvertent low-resistance path can pass current at levels that exceed the tolerance of the circuitry carrying the path. Consequently, such large currents can generate high levels of heat, ultimately resulting in cessation of circuit functions and even permanent destruction of the circuit.
Latch-up typically occurs as a result of the proximate locations of circuits, circuit components and portions of circuit components, which tend to be spaced in close proximity due to the high-density requirements of semiconductor devices. For example, in the design of complimentary metal-oxide semiconductor (CMOS) devices, there are complementary parasitic bipolar transistor structures that are in close proximity to one another. The close proximity allows the complimentary parasitic bipolar structures to interact electrically to form device structures that behave like pnpn diodes. Normally, such diodes are reverse-biased. However, in the presence of certain operating conditions, such as transient displacement currents, terminal over-voltage stress, ionizing radiation, or impact ionization by hot electrons, a normally reverse-biased diode becomes a forward-biased diode. Once the device becomes forward biased, current flows freely between the nodes of the device. As long as sufficient power is supplied, the device remains in the xe2x80x9cONxe2x80x9d state and exhibits latch-up. For additional details concerning the mathematics of, and efforts to overcome, the latch-up problem, reference may be made to various references such as R. R. Troutman, Latchup in CMOS Technologyxe2x80x94The Problem and its Cure, Kluwer Academic Publishers, Boston, Mass., 1986, and S. Wolf, Silicon Processing for the VLSI Era- Volume 11, Lattice Press, Sunset Beach, Calif. 1990, each of which is incorporated herein by reference.
Problems associated with ESD and latch-up continue to inhibit the performance and reliability of semiconductor devices, and problems associated with ESD in standard digital CMOS processes has been particularly difficult to address. In addition, while attempts to overcome latch-up problems have been successful to various levels of degree, as addressed in the above-cited references, latch-up continues to be a problem in semiconductor devices.
The present invention makes possible the protection against electro-static charge, latch-up and other operational conditions that can potentially inhibit performance of and/or cause harm to semiconductor devices, and addresses problems stated in the Background hereinabove. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention a semiconductor device comprises an input pad and a protection circuit. The protection circuit includes a first circuit coupled to the input pad and is adapted to effect voltage discharge in response to voltage at the pad reaching a threshold. The first circuit is configured in a first configuration for a power-up mode and in a second configuration in a power-down mode, each configuration exhibiting a different voltage discharge threshold selection. The device exhibits resistance to a tendency to latch-up, and is applicable to semiconductor devices including those exhibiting standard digital CMOS processes.
In another example embodiment of the present invention, a semiconductor device includes the protection circuit described hereinabove, coupled to a second circuit adapted to discharge voltage when voltage at the input pad is above a junction breakdown voltage for an input buffer to which the circuit is applicable.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.